Location:
Search - ddr test
Search list
Description: arm控制FPGA的DDR测试代码，共享一下-arm control FPGA DDR test code sharing what
Platform: |
Size: 2385568 |
Author: yourname |
Hits:
Description: pnx1500 ddr test demo
Platform: |
Size: 28742 |
Author: 曾宏 |
Hits:
Description: This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec
Platform: |
Size: 114780 |
Author: king.xia |
Hits:
Description: arm控制FPGA的DDR测试代码，共享一下-arm control FPGA DDR test code sharing what
Platform: |
Size: 2384896 |
Author: yourname |
Hits:
Description: pnx1500 ddr test demo
Platform: |
Size: 28672 |
Author: 曾宏 |
Hits:
Description: ddr and sdram memory check,ddr and sdram memory check-ddr sdram memory and check, ddr sdram memory check and
Platform: |
Size: 136192 |
Author: wangdong |
Hits:
Description: This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2
Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM.
As of this time, the DDR interface only works up to 120 MHz.
At 130, DDR data can be read but not written.
NOTE: the test bench cannot be simulated with DDR enabled
because the Altera pads do not have the correct delay models.
* How to program the flash prom with a FPGA programming file
1. Create a hex file of the programming file with Quartus.
2. Convert it to srecord and adjust the load address:
objcopy--adjust-vma=0x800000 output_file.hexout-O srec fpga.srec
3. Program the flash memory using grmon:
flash erase 0x800000 0xb00000
flash load fpga.srec
Platform: |
Size: 114688 |
Author: |
Hits:
Description: 开发Inetl IXP2400平台所必须的硬件诊断和测试程序。该软件包支持的功能包括CPU基本功能检测，串行通讯测试，以太网测试，DDR测试，QDR存储器测试，PCI总线检测等等。-Inetl IXP2400 development platform necessary hardware diagnostic and test procedures. The package features include CPU support the basic functions of detection, serial communications testing, Ethernet, DDR test, QDR memory test, PCI bus detection and so on.
Platform: |
Size: 1758208 |
Author: saishindou |
Hits:
Description: ddr 2 接口读写测试模块
ddr 2 接口读写测试模块 -ddr 2 interface test module ddr 2 read and write interface to read and write test module
Platform: |
Size: 125952 |
Author: 骑士 |
Hits:
Description: davincievm 6446 記憶體DDR撿測-davincievm 6446 seized DDR memory test
Platform: |
Size: 48128 |
Author: 謝震威 |
Hits:
Description: DDR SDRAM控制器的VHDL源代码，含详细设计文档。
The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock
Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS),
and Digital Frequency Synthesis (DFS) functions. This application note describes a controller
design for a 16-bit DDR SDRAM. The application note and reference design are enhanced
versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz,
16-bit data changes at both clock edges. The reference design is fully synthesizable and
achieves 133 MHz performance with automatic place and route tools.-DDR SDRAM controller VHDL source code, including detailed design documents. The DDR, DCM, and SelectI/O
Platform: |
Size: 132096 |
Author: xbl |
Hits:
Description: ccs下对dm6446的测试程序，能够检测ddr,nandflash,uart,usb等硬件电路的裸板测试代码，包含库文件，板级gel文件，开发环境在TI ccs3.3下。-ccs on DM6446 testing procedures can detect ddr, nandflash, uart, usb hardware such as the bare circuit board to test the code, including library files, board-level gel documentation, development environment in the next TI ccs3.3.
Platform: |
Size: 3568640 |
Author: 王枫 |
Hits:
Description: 合众达DM6446试验箱学习实验源代码 ddr内存实验-the experimental source code DM6446 chamber ddr memory test
Platform: |
Size: 71680 |
Author: Daniel |
Hits:
Description: 该程序是TI的达芬奇处理器DM6467开发板的DDR测试程序，该程序的开发环境是CCS3.3，使用的编程语言是C-The program is for TI s DaVinci processor DM6467 development board test program of DDR , the program s development environment is CCS3.3, using the programming language is C
Platform: |
Size: 58368 |
Author: 何波 |
Hits:
Description: test bench for ddr 1
Platform: |
Size: 2048 |
Author: shiva |
Hits:
Description: DM365的ddr测试和板子调试程序，最后调试顺利通过-DM365 ddr test and debug programs and at last successful
Platform: |
Size: 40960 |
Author: 蔣伊樂 |
Hits:
Description: 达芬奇系列开发板，ddr测试程序，用于检测Dsp和ddr之间的通路正常工作-Da Vinci series development board, DDR test program, used to detect between Dsp and DDR pathways to work normally
Platform: |
Size: 57344 |
Author: 卡卡罗特 |
Hits:
Description: test ddr to ddr performance
Platform: |
Size: 1024 |
Author: litterfish
|
Hits:
Description: DM36x平台下的DDR测试程序（c源码），包括对DDR的写入和读出。(The DDR test program (c source code) under the DM36x platform, including the writing and reading of the DDR.)
Platform: |
Size: 40960 |
Author: 一夏 |
Hits:
Description: DDR 压力测试 ，针对imx6平台的DDR压力测试工具(DDR test for imx6 platform)
Platform: |
Size: 1767424 |
Author: 小石头初见 |
Hits: